1. Field of the Invention
The present invention relates to image-signal processing apparatuses which clamp an analog image signal, such as Y, Pb, and Pr signals, and then convert it to a digital image signal, and image display apparatuses, such as TV-camera viewfinders, which use the image-signal processing apparatuses.
2. Description of the Related Art
FIG. 10 is a block diagram of an image-signal processing apparatus used in a conventional image display apparatus, such as a TV-camera viewfinder.
In FIG. 10, analog Y, Pb, and Pr signals to which matrix conversion has been applied by a HDTV (Hi-Vision) method are input from a previous-stage TV camera (not shown) or others to terminals 101, 104, and 107. The Y signal is input to a synchronization separation circuit 111 to be separated into a horizontal synchronizing signal Hs and a vertical synchronizing signal Vs. A clamp-pulse generation circuit 110 generates a clamp pulse according to the horizontal synchronizing signal Hs. A clock generation circuit 118 generates a clock pulse CLK in synchronization with the horizontal synchronizing signal Hs. In the figure, thick lines indicate data bases, and solid lines indicate control buses.
The input Y, Pb, and Pr signals are clamped at a DC level with the use of the clamp pulse CLP by clamp circuits 102, 105, and 108; their clamp outputs 112, 114, and 116 are A/D-converted by quantization circuit 103, 106, and 109 to form a digital Y signal 113, a digital Pb signal 115, and a digital Pr signal 117; and they are input to an inverse matrix conversion circuit 108.
The inverse matrix conversion circuit 108 applies inverse matrix calculation processing to the digital Y, Pb, and Pr signals to generate digital R, G, and B signals and to output them at output terminals 120, 121, and 122.G=k(Y−0.187 Pb−0.468 Pr)B=k(Y+0.1856 Pb)  (1)R=k(Y+1.575 Pr)
These R, G, and B signals are processed by a subsequent-stage display processing circuit (not shown), and displayed on a liquid-crystal display apparatus (not shown) or others.
FIG. 11 shows unclamped Y, Pb, and Pr signals and clamp pulses CLP in a case in which a color bar is displayed, with arrows indicating the pedestal levels of the signals. In this figure, the back porch of each signal has the same level as the pedestal, which is an ideal condition. In an actual case, the Y, Pb, and Pr signals have indefinite DC levels.
As shown in the figure, the Y signal has an image component at the positive side of the pedestal level, and the Pb and Pr signals have image components at both sides of the pedestal level. A level of each signal, close to the pedestal level is clamped to a predetermined level by a clamp pulse CLP.
FIG. 12 shows the relationship between clamped Y, Pb, and Pr signals (the clamp outputs 112, 114, and 116 in FIG. 10) and calculation reference values used for A/D conversion to eight-bit digital signals.
As shown in the figure, when the Y signal is A/D converted such that the pedestal level is set to the minimum digital value Ref—L, “0” and the maximum digital value Ref—H is set to “255,” the maximum dynamic range is obtained. When the Pb and Pr signals are A/D converted such that the minimum digital value Ref—L is set to “0,” the maximum digital value Ref—H is set to “255,” and the pedestal level is set to “127,” the maximum dynamic ranges are obtained.
In the conventional image-signal processing apparatus, however, an analog signal system and a digital signal system have the following problem.
FIG. 13 shows the structure of the conventional clamp circuit 102 shown in FIG. 12. The other clamp circuits 105 and 108 have the same structure.
In FIG. 13, the clamp circuit 102 is basically formed of the input terminal 101 to which the Y signal is input, an input terminal 123 to which the clamp pulse CLP is input, a coupling capacitor C201, a switch SW203, a power source E209, an amplifier U208, and an output terminal 124. In addition to these components, parasitic resistors R202, R204, and R206, and parasitic capacitors C205 and C207 connected by dotted lines also exist.
In FIG. 13, after the switch SW203 is closed for the pulse width of the clamp pulse CLP to charge the capacitor C201, the switch SW203 is opened. The pedestal level of the Y signal is clamped to the voltage Vp of the power source E209.
Since the actual circuit includes the parasitic resistors R202, R204, and R206, however, charges may flow in or out from the capacitor C201 due to the leakage effect of the parasitic resistors. In addition, since there are the parasitic capacitors C205 and C207, the charges of the capacitor C201 are distributed. Especially, the capacitor C205 connected in parallel to the switch SW203 is not charged at all when the switch SW203 is closed, as if the capacitor C205 nominally did not exist, but it absorbs charges of the capacitor C201 when the switch SW203 is opened, as if it suddenly appeared.
In the conventional clamp circuit, a voltage shift ΔVp shown in FIG. 14 occurs in the clamp voltage Vp due to the parasitic resistors and parasitic capacitors. FIG. 14 shows that the actual clamp voltage is shifted from the target voltage by ΔVp. When this voltage shift is A/D converted by a quantization circuit, the following shift “err” appears in the A/D conversion output.err=−ΔVp/(Ref—H−Ref—L)×255
When inverse matrix conversion is applied to digital Y, Pb, and Pr signals having such a clamp-voltage shift “err,” by the calculation expressed by (1) to convert them to R, G, and B signals, because the calculation coefficients differ among the R, G, and B signals, the shift appears differently in the signals, causing deterioration in color balance.
To eliminate the effect of the parasitic resistors and parasitic capacitors, a method has been conventionally considered in which the output voltage is fed back to the power source E209 in FIG. 13. An attempt is also made to reduce the parasitic resistors and parasitic capacitors themselves as much as possible. Any method, however, increases cost.
Further, there was conventionally a problem of precision in a quantization circuit.
FIG. 15 shows the structure of the quantization circuit 103 shown in FIG. 10. The other quantization circuits 106 and 109 have the same structure.
In FIG. 15, the quantization circuit 103 includes an A/D converter 103a. The target voltage is input from the clamp circuit 102, which is the previous-stage circuit, to an input terminal 125, and an A/D conversion output (digital Y signal) is obtained at an output terminal 126. The reference voltage Vref—H and the reference voltage Vref—L are applied to the A/D converter 103a to obtain the digital value “255” and the digital value “0” respectively.
When the reference voltages Vref—H and Vref—L and a voltage of (Vref—H+Vref—L)/2, which is used to obtain the intermediate digital value “127,” are input as the target voltage, the A/D conversion outputs obtained at the output terminal 126 have shifts of α, β, and γ as shown in Table 2 due to variations in the precision of the A/D converter 103a.
TABLE 2OUTPUTTARGET VOLTAGEIDEAL CASEACTUAL CASEVref—H255255 − α(Vref—H + Vref—L)/2127127 ± βVref—L0 0 + γ
To increase the precision of the A/D converter 103a to eliminate the shifts α, β, and γ it is necessary that a high current flow into an analog part of the A/D converter 103a. As a result, power consumption increases. In addition, a precise A/D converter is expensive. As described above, conventionally, a large amount of cost and a high power consumption are required to prevent pedestal-level values obtained after quantization from shifting.